Nowadays, a trend of a shape of electronic products is toward thin and slim. Multilayer circuit boards (such as package substrate, printed circuit board, high density interconnect (HDI), probe card carrier board, etc.) serve as carrier boards for integrating electronic components in the electronic products. A trace density and an integrated density of interlayer interconnections of the multilayer circuit board will directly affect an electrical performance and a thickness of the electronic product, which is a factor deciding a degree of miniature of the product. Therefore, in manufacturing the multilayer circuit board, a design and fabrication of stacked via holes have become a developing focus of the interlayer interconnection technology of the multilayer circuit board.
The stacked via holes are interfaces created by metal deposition for electrically connecting upper and lower circuit boards. Please refer to FIG. 1, which shows a schematic diagram of a multilayer circuit board 10 of the prior art. The multilayer circuit board 10 includes a base plate 11, a first board 12, a second board 13, a first conductive layer 16, and a second conductive layer 17. The first board 12 is provided with a first conductive via hole 14, and the second board 13 is provided with a second conductive via hole 15. The first conductive layer 16 fills the first conductive via hole 14, and the second conductive layer 17 fills the second conductive via hole 15. The second board 13 is stacked on the first board 12, and the first board 12 and the second board 13 are electrically contacted to each other by the first conductive layer 16 and the second conductive layer 17 which are in contact with each other. In the multilayer circuit board 10 of the prior art, the connecting part 18 of the first conductive layer 16 and the second conductive layer 17 is a two-dimensional plane, that is, an X-Y plane.
However, during manufacturing, the first conductive layer 16 and the second conductive layer 17 are not formed continuously by the same process. Instead, the first conductive layer 16 is formed first, and the second conductive layer 17 is sequentially formed by another process. Therefore, the connecting part 18 interconnecting the first conductive layer 16 and the second conductive layer 17 is easily to break, causing the stacked via holes to be disconnected and accordingly a resistance value between the first conductive layer 16 and the second conductive layer 17 to be large. Specifically, please refer to FIG. 2, which is a schematic diagram showing the first conductive layer 16 and the second conductive layer 17 of the multilayer circuit board 10 of FIG. 1 being separated from each other. Material of a conductive layer and material of the first board 12 and the second board 13 have different thermal expansion coefficients. When the multilayer circuit board 10 is in a critical condition (such as in a high temperature or high humidity environment, or being subjected to thermal shock during the process), the first conductive layer 16 and the second conductive layer 17 will deform, and the first conductive layer 16 and the second conductive layer 17 will separate from each other around the connecting part 18.
As shown in FIG. 2, at the disconnected connecting part 18, a plurality of pores 19 may be formed between the first conductive layer 16 and the second conductive layer 17, thereby forming an open circuit. Thus, the resistance value between the first conductive layer 16 and the second conductive layer 17 is increased, thereby decreasing an electrical performance of the multilayer circuit board 10.
Accordingly, it is necessary to provide a multilayer circuit board and manufacturing method thereof to solve the technical problem in the prior art.